URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] - Rev 34

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Rev	Log message	Author	Age	Path
34	added	unneback	5352d 09h	/versatile_mem_ctrl/
33	work for limited test case, no cke inhibit for fifo empty	unneback	5352d 12h	/versatile_mem_ctrl/
32	Updated the testbench to match the new wishbone interface.	mikaeljf	5355d 16h	/versatile_mem_ctrl/
31	Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts.	mikaeljf	5357d 09h	/versatile_mem_ctrl/
30	Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts.	mikaeljf	5357d 09h	/versatile_mem_ctrl/
29	Adapted the test bench to the new wishbone interface.	mikaeljf	5361d 09h	/versatile_mem_ctrl/
28	Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'.	mikaeljf	5361d 11h	/versatile_mem_ctrl/
27		unneback	5365d 02h	/versatile_mem_ctrl/
26	compiles OK, not simulated	unneback	5367d 01h	/versatile_mem_ctrl/
25		unneback	5367d 04h	/versatile_mem_ctrl/
24	Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions.	mikaeljf	5367d 15h	/versatile_mem_ctrl/
23	Removed redundant code.	mikaeljf	5375d 08h	/versatile_mem_ctrl/
22	Updated the Altera timing constraints file, also minor updates of defines file and Makefile.	mikaeljf	5377d 04h	/versatile_mem_ctrl/
21	Updated the Altera timing constraints file (.sdc).	mikaeljf	5381d 07h	/versatile_mem_ctrl/
20	Minor update of sdc-file.	mikaeljf	5383d 09h	/versatile_mem_ctrl/
19	Added do-file for Modelsim waveform viewer.	mikaeljf	5389d 13h	/versatile_mem_ctrl/
18	Updated the rtl/verilog Makefile and the bench Makefile.	mikaeljf	5390d 10h	/versatile_mem_ctrl/
17	Modified rtl Makefile and tb_defines.v	mikaeljf	5393d 09h	/versatile_mem_ctrl/
16	Added fizzim.pl	mikaeljf	5393d 09h	/versatile_mem_ctrl/
15	Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera.	mikaeljf	5394d 10h	/versatile_mem_ctrl/

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Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] - Rev 34

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