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Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] - Rev 35

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Rev Log message Author Age Path
35 work for limited test case unneback 5188d 21h /versatile_mem_ctrl/
34 added unneback 5188d 21h /versatile_mem_ctrl/
33 work for limited test case, no cke inhibit for fifo empty unneback 5189d 00h /versatile_mem_ctrl/
32 Updated the testbench to match the new wishbone interface. mikaeljf 5192d 04h /versatile_mem_ctrl/
31 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5193d 21h /versatile_mem_ctrl/
30 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5193d 21h /versatile_mem_ctrl/
29 Adapted the test bench to the new wishbone interface. mikaeljf 5197d 21h /versatile_mem_ctrl/
28 Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'. mikaeljf 5197d 23h /versatile_mem_ctrl/
27 unneback 5201d 14h /versatile_mem_ctrl/
26 compiles OK, not simulated unneback 5203d 13h /versatile_mem_ctrl/
25 unneback 5203d 16h /versatile_mem_ctrl/
24 Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions. mikaeljf 5204d 03h /versatile_mem_ctrl/
23 Removed redundant code. mikaeljf 5211d 20h /versatile_mem_ctrl/
22 Updated the Altera timing constraints file, also minor updates of defines file and Makefile. mikaeljf 5213d 16h /versatile_mem_ctrl/
21 Updated the Altera timing constraints file (.sdc). mikaeljf 5217d 19h /versatile_mem_ctrl/
20 Minor update of sdc-file. mikaeljf 5219d 21h /versatile_mem_ctrl/
19 Added do-file for Modelsim waveform viewer. mikaeljf 5226d 01h /versatile_mem_ctrl/
18 Updated the rtl/verilog Makefile and the bench Makefile. mikaeljf 5226d 22h /versatile_mem_ctrl/
17 Modified rtl Makefile and tb_defines.v mikaeljf 5229d 21h /versatile_mem_ctrl/
16 Added fizzim.pl mikaeljf 5229d 22h /versatile_mem_ctrl/

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