OpenCores
URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] - Rev 37

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
37 unneback 5259d 13h /versatile_mem_ctrl/
36 unneback 5259d 14h /versatile_mem_ctrl/
35 work for limited test case unneback 5259d 21h /versatile_mem_ctrl/
34 added unneback 5259d 22h /versatile_mem_ctrl/
33 work for limited test case, no cke inhibit for fifo empty unneback 5260d 00h /versatile_mem_ctrl/
32 Updated the testbench to match the new wishbone interface. mikaeljf 5263d 04h /versatile_mem_ctrl/
31 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5264d 21h /versatile_mem_ctrl/
30 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5264d 21h /versatile_mem_ctrl/
29 Adapted the test bench to the new wishbone interface. mikaeljf 5268d 21h /versatile_mem_ctrl/
28 Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'. mikaeljf 5268d 23h /versatile_mem_ctrl/
27 unneback 5272d 14h /versatile_mem_ctrl/
26 compiles OK, not simulated unneback 5274d 13h /versatile_mem_ctrl/
25 unneback 5274d 16h /versatile_mem_ctrl/
24 Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions. mikaeljf 5275d 03h /versatile_mem_ctrl/
23 Removed redundant code. mikaeljf 5282d 20h /versatile_mem_ctrl/
22 Updated the Altera timing constraints file, also minor updates of defines file and Makefile. mikaeljf 5284d 16h /versatile_mem_ctrl/
21 Updated the Altera timing constraints file (.sdc). mikaeljf 5288d 19h /versatile_mem_ctrl/
20 Minor update of sdc-file. mikaeljf 5290d 21h /versatile_mem_ctrl/
19 Added do-file for Modelsim waveform viewer. mikaeljf 5297d 01h /versatile_mem_ctrl/
18 Updated the rtl/verilog Makefile and the bench Makefile. mikaeljf 5297d 22h /versatile_mem_ctrl/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.