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Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] - Rev 43

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Rev Log message Author Age Path
43 unneback 5197d 16h /versatile_mem_ctrl/
42 added pipeline stage for egress FIFO readot unneback 5198d 00h /versatile_mem_ctrl/
41 Added two alternate data capture functions. mikaeljf 5198d 08h /versatile_mem_ctrl/
40 updated fifo interfaces with re/rd and we/wr unneback 5198d 15h /versatile_mem_ctrl/
39 updated FIFO and SDR 16 unneback 5199d 02h /versatile_mem_ctrl/
38 casex in rw state to save logic unneback 5201d 10h /versatile_mem_ctrl/
37 unneback 5202d 00h /versatile_mem_ctrl/
36 unneback 5202d 01h /versatile_mem_ctrl/
35 work for limited test case unneback 5202d 08h /versatile_mem_ctrl/
34 added unneback 5202d 08h /versatile_mem_ctrl/
33 work for limited test case, no cke inhibit for fifo empty unneback 5202d 10h /versatile_mem_ctrl/
32 Updated the testbench to match the new wishbone interface. mikaeljf 5205d 14h /versatile_mem_ctrl/
31 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5207d 07h /versatile_mem_ctrl/
30 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5207d 07h /versatile_mem_ctrl/
29 Adapted the test bench to the new wishbone interface. mikaeljf 5211d 08h /versatile_mem_ctrl/
28 Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'. mikaeljf 5211d 09h /versatile_mem_ctrl/
27 unneback 5215d 01h /versatile_mem_ctrl/
26 compiles OK, not simulated unneback 5217d 00h /versatile_mem_ctrl/
25 unneback 5217d 03h /versatile_mem_ctrl/
24 Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions. mikaeljf 5217d 14h /versatile_mem_ctrl/

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