URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] - Rev 46

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Rev	Log message	Author	Age	Path
46	cosmetic updates	unneback	5253d 05h	/versatile_mem_ctrl/
45	added	unneback	5253d 07h	/versatile_mem_ctrl/
44	registered row comparison	unneback	5255d 07h	/versatile_mem_ctrl/
43		unneback	5255d 13h	/versatile_mem_ctrl/
42	added pipeline stage for egress FIFO readot	unneback	5255d 21h	/versatile_mem_ctrl/
41	Added two alternate data capture functions.	mikaeljf	5256d 04h	/versatile_mem_ctrl/
40	updated fifo interfaces with re/rd and we/wr	unneback	5256d 11h	/versatile_mem_ctrl/
39	updated FIFO and SDR 16	unneback	5256d 23h	/versatile_mem_ctrl/
38	casex in rw state to save logic	unneback	5259d 06h	/versatile_mem_ctrl/
37		unneback	5259d 21h	/versatile_mem_ctrl/
36		unneback	5259d 21h	/versatile_mem_ctrl/
35	work for limited test case	unneback	5260d 05h	/versatile_mem_ctrl/
34	added	unneback	5260d 05h	/versatile_mem_ctrl/
33	work for limited test case, no cke inhibit for fifo empty	unneback	5260d 07h	/versatile_mem_ctrl/
32	Updated the testbench to match the new wishbone interface.	mikaeljf	5263d 11h	/versatile_mem_ctrl/
31	Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts.	mikaeljf	5265d 04h	/versatile_mem_ctrl/
30	Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts.	mikaeljf	5265d 04h	/versatile_mem_ctrl/
29	Adapted the test bench to the new wishbone interface.	mikaeljf	5269d 04h	/versatile_mem_ctrl/
28	Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'.	mikaeljf	5269d 06h	/versatile_mem_ctrl/
27		unneback	5272d 22h	/versatile_mem_ctrl/

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Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] - Rev 46

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