URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] - Rev 49

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Rev	Log message	Author	Age	Path
49	Added versatile_fifo_dual_port_ram_dc_sw.v rule to makefile, getting it from versatile fifo project	julius	5319d 12h	/versatile_mem_ctrl/
48	dq_oe fix	unneback	5319d 12h	/versatile_mem_ctrl/
47	support for registered outputs on ras, cas and we	unneback	5319d 12h	/versatile_mem_ctrl/
46	cosmetic updates	unneback	5319d 13h	/versatile_mem_ctrl/
45	added	unneback	5319d 16h	/versatile_mem_ctrl/
44	registered row comparison	unneback	5321d 15h	/versatile_mem_ctrl/
43		unneback	5321d 21h	/versatile_mem_ctrl/
42	added pipeline stage for egress FIFO readot	unneback	5322d 05h	/versatile_mem_ctrl/
41	Added two alternate data capture functions.	mikaeljf	5322d 12h	/versatile_mem_ctrl/
40	updated fifo interfaces with re/rd and we/wr	unneback	5322d 19h	/versatile_mem_ctrl/
39	updated FIFO and SDR 16	unneback	5323d 07h	/versatile_mem_ctrl/
38	casex in rw state to save logic	unneback	5325d 14h	/versatile_mem_ctrl/
37		unneback	5326d 05h	/versatile_mem_ctrl/
36		unneback	5326d 05h	/versatile_mem_ctrl/
35	work for limited test case	unneback	5326d 13h	/versatile_mem_ctrl/
34	added	unneback	5326d 13h	/versatile_mem_ctrl/
33	work for limited test case, no cke inhibit for fifo empty	unneback	5326d 15h	/versatile_mem_ctrl/
32	Updated the testbench to match the new wishbone interface.	mikaeljf	5329d 19h	/versatile_mem_ctrl/
31	Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts.	mikaeljf	5331d 12h	/versatile_mem_ctrl/
30	Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts.	mikaeljf	5331d 12h	/versatile_mem_ctrl/

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Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] - Rev 49

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