URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] - Rev 58

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Rev	Log message	Author	Age	Path
58	sdr_16 fixes for timing - extra egress register stage, appropriate changes in sdr_16 fsm	julius	5213d 02h	/versatile_mem_ctrl/
57	added support for early termination of burst access	unneback	5214d 05h	/versatile_mem_ctrl/
56	corrected fifo_rd_data in state w4d	unneback	5215d 22h	/versatile_mem_ctrl/
55	Fixed up sdr16 dqm output	julius	5216d 16h	/versatile_mem_ctrl/
54	dqm moved into FSM	unneback	5217d 13h	/versatile_mem_ctrl/
53		unneback	5217d 14h	/versatile_mem_ctrl/
52	act exit for read updated	unneback	5218d 15h	/versatile_mem_ctrl/
51	act exit for read updated	unneback	5218d 15h	/versatile_mem_ctrl/
50	Fixed up make file - THIS MAY BREAK THINGS, but it's a lot neater and easier to use, also dependencies are now properly configured, and we don't remake things unecessarily	julius	5218d 18h	/versatile_mem_ctrl/
49	Added versatile_fifo_dual_port_ram_dc_sw.v rule to makefile, getting it from versatile fifo project	julius	5218d 19h	/versatile_mem_ctrl/
48	dq_oe fix	unneback	5218d 19h	/versatile_mem_ctrl/
47	support for registered outputs on ras, cas and we	unneback	5218d 20h	/versatile_mem_ctrl/
46	cosmetic updates	unneback	5218d 21h	/versatile_mem_ctrl/
45	added	unneback	5218d 23h	/versatile_mem_ctrl/
44	registered row comparison	unneback	5220d 23h	/versatile_mem_ctrl/
43		unneback	5221d 04h	/versatile_mem_ctrl/
42	added pipeline stage for egress FIFO readot	unneback	5221d 12h	/versatile_mem_ctrl/
41	Added two alternate data capture functions.	mikaeljf	5221d 20h	/versatile_mem_ctrl/
40	updated fifo interfaces with re/rd and we/wr	unneback	5222d 03h	/versatile_mem_ctrl/
39	updated FIFO and SDR 16	unneback	5222d 14h	/versatile_mem_ctrl/

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Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] - Rev 58

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