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[/] [versatile_mem_ctrl/] - Rev 59

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Rev Log message Author Age Path
59 counter changed to shift register unneback 5203d 12h /versatile_mem_ctrl/
58 sdr_16 fixes for timing - extra egress register stage, appropriate changes in sdr_16 fsm julius 5204d 13h /versatile_mem_ctrl/
57 added support for early termination of burst access unneback 5205d 15h /versatile_mem_ctrl/
56 corrected fifo_rd_data in state w4d unneback 5207d 08h /versatile_mem_ctrl/
55 Fixed up sdr16 dqm output julius 5208d 03h /versatile_mem_ctrl/
54 dqm moved into FSM unneback 5209d 00h /versatile_mem_ctrl/
53 unneback 5209d 00h /versatile_mem_ctrl/
52 act exit for read updated unneback 5210d 01h /versatile_mem_ctrl/
51 act exit for read updated unneback 5210d 02h /versatile_mem_ctrl/
50 Fixed up make file - THIS MAY BREAK THINGS, but it's a lot neater and easier to use, also dependencies are now properly configured, and we don't remake things unecessarily julius 5210d 04h /versatile_mem_ctrl/
49 Added versatile_fifo_dual_port_ram_dc_sw.v rule to makefile, getting it from versatile fifo project julius 5210d 06h /versatile_mem_ctrl/
48 dq_oe fix unneback 5210d 06h /versatile_mem_ctrl/
47 support for registered outputs on ras, cas and we unneback 5210d 06h /versatile_mem_ctrl/
46 cosmetic updates unneback 5210d 07h /versatile_mem_ctrl/
45 added unneback 5210d 09h /versatile_mem_ctrl/
44 registered row comparison unneback 5212d 09h /versatile_mem_ctrl/
43 unneback 5212d 15h /versatile_mem_ctrl/
42 added pipeline stage for egress FIFO readot unneback 5212d 23h /versatile_mem_ctrl/
41 Added two alternate data capture functions. mikaeljf 5213d 06h /versatile_mem_ctrl/
40 updated fifo interfaces with re/rd and we/wr unneback 5213d 13h /versatile_mem_ctrl/

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