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[/] [versatile_mem_ctrl/] - Rev 68

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Rev Log message Author Age Path
68 cleaqnup unneback 5186d 15h /versatile_mem_ctrl/
67 added FSM for wb if unneback 5186d 15h /versatile_mem_ctrl/
66 unneback 5186d 18h /versatile_mem_ctrl/
65 added unneback 5186d 18h /versatile_mem_ctrl/
64 Changed sdr 16 FSM to use defines instead of parameters which were somehow screwing up synplify, reinstated used of sdr_16_defines.v file julius 5187d 17h /versatile_mem_ctrl/
63 Fixed a couple of sdr_16 bugs to do with tracking of opened banks julius 5188d 01h /versatile_mem_ctrl/
62 Added note to sdr_16_defines.v asking if it's still used julius 5188d 03h /versatile_mem_ctrl/
61 Fixed blocking/nonblocking assign issue in sdr_16 fsm julius 5192d 01h /versatile_mem_ctrl/
60 Added synthesis directives ensuring registering of right signals in IOBs for sdr16 controller. Removed comment stripping from vppreproc command for sdr_16 creation. julius 5192d 01h /versatile_mem_ctrl/
59 counter changed to shift register unneback 5192d 03h /versatile_mem_ctrl/
58 sdr_16 fixes for timing - extra egress register stage, appropriate changes in sdr_16 fsm julius 5193d 04h /versatile_mem_ctrl/
57 added support for early termination of burst access unneback 5194d 06h /versatile_mem_ctrl/
56 corrected fifo_rd_data in state w4d unneback 5195d 23h /versatile_mem_ctrl/
55 Fixed up sdr16 dqm output julius 5196d 18h /versatile_mem_ctrl/
54 dqm moved into FSM unneback 5197d 15h /versatile_mem_ctrl/
53 unneback 5197d 15h /versatile_mem_ctrl/
52 act exit for read updated unneback 5198d 17h /versatile_mem_ctrl/
51 act exit for read updated unneback 5198d 17h /versatile_mem_ctrl/
50 Fixed up make file - THIS MAY BREAK THINGS, but it's a lot neater and easier to use, also dependencies are now properly configured, and we don't remake things unecessarily julius 5198d 19h /versatile_mem_ctrl/
49 Added versatile_fifo_dual_port_ram_dc_sw.v rule to makefile, getting it from versatile fifo project julius 5198d 21h /versatile_mem_ctrl/

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