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URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] - Rev 82

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Rev Log message Author Age Path
82 mikaeljf 5106d 22h /versatile_mem_ctrl/
81 mikaeljf 5107d 19h /versatile_mem_ctrl/
80 mikaeljf 5107d 20h /versatile_mem_ctrl/
79 Added defines that fix bugs with slow wishbone clocks doing burst writes julius 5145d 10h /versatile_mem_ctrl/
78 Burst writing working again, although its mostly hardcoded to burst 4. Also added a fix for when the RAM and bus clocks are about the same speed, to avoid buffer overrun julius 5147d 17h /versatile_mem_ctrl/
77 SDR 16 registering of current_fifo_empty signal in top, appropriate control alterations in fsm_sdr_16 julius 5155d 15h /versatile_mem_ctrl/
76 Changed SDR16 synthesis useioff location, fsm_wb acking logic, default SDR build is for 16m part now julius 5160d 16h /versatile_mem_ctrl/
75 mikaeljf 5160d 17h /versatile_mem_ctrl/
74 Minor update of rtl Makefile. mikaeljf 5164d 16h /versatile_mem_ctrl/
73 Minor updates to fix lost revisions 69 and 70. mikaeljf 5164d 17h /versatile_mem_ctrl/
72 Restored lost revisions 69 and 70. mikaeljf 5164d 18h /versatile_mem_ctrl/
71 Replacing versatile_mem_ctrl_top with revisino 68 version but with top level ack fix. May lose some of revision 69 and 70 changes julius 5164d 19h /versatile_mem_ctrl/
70 mikaeljf 5168d 01h /versatile_mem_ctrl/
69 mikaeljf 5168d 22h /versatile_mem_ctrl/
68 cleaqnup unneback 5170d 10h /versatile_mem_ctrl/
67 added FSM for wb if unneback 5170d 10h /versatile_mem_ctrl/
66 unneback 5170d 13h /versatile_mem_ctrl/
65 added unneback 5170d 13h /versatile_mem_ctrl/
64 Changed sdr 16 FSM to use defines instead of parameters which were somehow screwing up synplify, reinstated used of sdr_16_defines.v file julius 5171d 12h /versatile_mem_ctrl/
63 Fixed a couple of sdr_16 bugs to do with tracking of opened banks julius 5171d 20h /versatile_mem_ctrl/

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