URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] - Rev 88

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Rev	Log message	Author	Age	Path
88		unneback	5204d 13h	/versatile_mem_ctrl/
87		unneback	5204d 13h	/versatile_mem_ctrl/
86		mikaeljf	5256d 20h	/versatile_mem_ctrl/
85	Added a versatile_mem_ctrl specific version of the flag generation module in the versatile fifo.	mikaeljf	5257d 20h	/versatile_mem_ctrl/
84		mikaeljf	5261d 19h	/versatile_mem_ctrl/
83		mikaeljf	5262d 14h	/versatile_mem_ctrl/
82		mikaeljf	5262d 18h	/versatile_mem_ctrl/
81		mikaeljf	5263d 15h	/versatile_mem_ctrl/
80		mikaeljf	5263d 16h	/versatile_mem_ctrl/
79	Added defines that fix bugs with slow wishbone clocks doing burst writes	julius	5301d 06h	/versatile_mem_ctrl/
78	Burst writing working again, although its mostly hardcoded to burst 4. Also added a fix for when the RAM and bus clocks are about the same speed, to avoid buffer overrun	julius	5303d 13h	/versatile_mem_ctrl/
77	SDR 16 registering of current_fifo_empty signal in top, appropriate control alterations in fsm_sdr_16	julius	5311d 11h	/versatile_mem_ctrl/
76	Changed SDR16 synthesis useioff location, fsm_wb acking logic, default SDR build is for 16m part now	julius	5316d 12h	/versatile_mem_ctrl/
75		mikaeljf	5316d 13h	/versatile_mem_ctrl/
74	Minor update of rtl Makefile.	mikaeljf	5320d 12h	/versatile_mem_ctrl/
73	Minor updates to fix lost revisions 69 and 70.	mikaeljf	5320d 13h	/versatile_mem_ctrl/
72	Restored lost revisions 69 and 70.	mikaeljf	5320d 14h	/versatile_mem_ctrl/
71	Replacing versatile_mem_ctrl_top with revisino 68 version but with top level ack fix. May lose some of revision 69 and 70 changes	julius	5320d 15h	/versatile_mem_ctrl/
70		mikaeljf	5323d 21h	/versatile_mem_ctrl/
69		mikaeljf	5324d 18h	/versatile_mem_ctrl/

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Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] - Rev 88

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