URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] - Rev 95

Rev	Log message	Author	Age	Path
95	new files	unneback	5060d 23h	/versatile_mem_ctrl/
94	new TB	unneback	5069d 07h	/versatile_mem_ctrl/
93		unneback	5080d 04h	/versatile_mem_ctrl/
92		unneback	5080d 04h	/versatile_mem_ctrl/
91		unneback	5080d 04h	/versatile_mem_ctrl/
90		unneback	5080d 04h	/versatile_mem_ctrl/
89		unneback	5080d 04h	/versatile_mem_ctrl/
88		unneback	5080d 04h	/versatile_mem_ctrl/
87		unneback	5080d 05h	/versatile_mem_ctrl/
86		mikaeljf	5132d 12h	/versatile_mem_ctrl/
85	Added a versatile_mem_ctrl specific version of the flag generation module in the versatile fifo.	mikaeljf	5133d 12h	/versatile_mem_ctrl/
84		mikaeljf	5137d 11h	/versatile_mem_ctrl/
83		mikaeljf	5138d 06h	/versatile_mem_ctrl/
82		mikaeljf	5138d 10h	/versatile_mem_ctrl/
81		mikaeljf	5139d 07h	/versatile_mem_ctrl/
80		mikaeljf	5139d 08h	/versatile_mem_ctrl/
79	Added defines that fix bugs with slow wishbone clocks doing burst writes	julius	5176d 22h	/versatile_mem_ctrl/
78	Burst writing working again, although its mostly hardcoded to burst 4. Also added a fix for when the RAM and bus clocks are about the same speed, to avoid buffer overrun	julius	5179d 05h	/versatile_mem_ctrl/
77	SDR 16 registering of current_fifo_empty signal in top, appropriate control alterations in fsm_sdr_16	julius	5187d 03h	/versatile_mem_ctrl/
76	Changed SDR16 synthesis useioff location, fsm_wb acking logic, default SDR build is for 16m part now	julius	5192d 04h	/versatile_mem_ctrl/