URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] - Rev 96

Rev	Log message	Author	Age	Path
96	doc update	unneback	5086d 03h	/versatile_mem_ctrl/
95	new files	unneback	5090d 16h	/versatile_mem_ctrl/
94	new TB	unneback	5099d 00h	/versatile_mem_ctrl/
93		unneback	5109d 22h	/versatile_mem_ctrl/
92		unneback	5109d 22h	/versatile_mem_ctrl/
91		unneback	5109d 22h	/versatile_mem_ctrl/
90		unneback	5109d 22h	/versatile_mem_ctrl/
89		unneback	5109d 22h	/versatile_mem_ctrl/
88		unneback	5109d 22h	/versatile_mem_ctrl/
87		unneback	5109d 22h	/versatile_mem_ctrl/
86		mikaeljf	5162d 05h	/versatile_mem_ctrl/
85	Added a versatile_mem_ctrl specific version of the flag generation module in the versatile fifo.	mikaeljf	5163d 05h	/versatile_mem_ctrl/
84		mikaeljf	5167d 04h	/versatile_mem_ctrl/
83		mikaeljf	5167d 23h	/versatile_mem_ctrl/
82		mikaeljf	5168d 04h	/versatile_mem_ctrl/
81		mikaeljf	5169d 00h	/versatile_mem_ctrl/
80		mikaeljf	5169d 01h	/versatile_mem_ctrl/
79	Added defines that fix bugs with slow wishbone clocks doing burst writes	julius	5206d 15h	/versatile_mem_ctrl/
78	Burst writing working again, although its mostly hardcoded to burst 4. Also added a fix for when the RAM and bus clocks are about the same speed, to avoid buffer overrun	julius	5208d 22h	/versatile_mem_ctrl/
77	SDR 16 registering of current_fifo_empty signal in top, appropriate control alterations in fsm_sdr_16	julius	5216d 20h	/versatile_mem_ctrl/