URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] - Rev 96

Rev	Log message	Author	Age	Path
96	doc update	unneback	5029d 18h	/versatile_mem_ctrl/
95	new files	unneback	5034d 07h	/versatile_mem_ctrl/
94	new TB	unneback	5042d 15h	/versatile_mem_ctrl/
93		unneback	5053d 12h	/versatile_mem_ctrl/
92		unneback	5053d 12h	/versatile_mem_ctrl/
91		unneback	5053d 12h	/versatile_mem_ctrl/
90		unneback	5053d 12h	/versatile_mem_ctrl/
89		unneback	5053d 12h	/versatile_mem_ctrl/
88		unneback	5053d 12h	/versatile_mem_ctrl/
87		unneback	5053d 12h	/versatile_mem_ctrl/
86		mikaeljf	5105d 20h	/versatile_mem_ctrl/
85	Added a versatile_mem_ctrl specific version of the flag generation module in the versatile fifo.	mikaeljf	5106d 20h	/versatile_mem_ctrl/
84		mikaeljf	5110d 19h	/versatile_mem_ctrl/
83		mikaeljf	5111d 14h	/versatile_mem_ctrl/
82		mikaeljf	5111d 18h	/versatile_mem_ctrl/
81		mikaeljf	5112d 15h	/versatile_mem_ctrl/
80		mikaeljf	5112d 16h	/versatile_mem_ctrl/
79	Added defines that fix bugs with slow wishbone clocks doing burst writes	julius	5150d 06h	/versatile_mem_ctrl/
78	Burst writing working again, although its mostly hardcoded to burst 4. Also added a fix for when the RAM and bus clocks are about the same speed, to avoid buffer overrun	julius	5152d 12h	/versatile_mem_ctrl/
77	SDR 16 registering of current_fifo_empty signal in top, appropriate control alterations in fsm_sdr_16	julius	5160d 11h	/versatile_mem_ctrl/