URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [tags/] [Rev1/] [sim/] - Rev 92

Rev	Log message	Author	Age	Path
92		unneback	5069d 19h	/versatile_mem_ctrl/tags/Rev1/sim/
86		mikaeljf	5122d 03h	/versatile_mem_ctrl/trunk/sim/
82		mikaeljf	5128d 01h	/versatile_mem_ctrl/trunk/sim/
80		mikaeljf	5128d 23h	/versatile_mem_ctrl/trunk/sim/
75		mikaeljf	5181d 20h	/versatile_mem_ctrl/trunk/sim/
70		mikaeljf	5189d 04h	/versatile_mem_ctrl/trunk/sim/
69		mikaeljf	5190d 00h	/versatile_mem_ctrl/trunk/sim/
31	Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts.	mikaeljf	5215d 19h	/versatile_mem_ctrl/trunk/sim/
28	Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'.	mikaeljf	5219d 21h	/versatile_mem_ctrl/trunk/sim/
19	Added do-file for Modelsim waveform viewer.	mikaeljf	5247d 23h	/versatile_mem_ctrl/trunk/sim/
15	Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera.	mikaeljf	5252d 20h	/versatile_mem_ctrl/trunk/sim/