URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [tags/] [Rev1/] [syn/] [altera/] - Rev 93

Rev	Log message	Author	Age	Path
93		unneback	5107d 03h	/versatile_mem_ctrl/tags/Rev1/syn/altera/
86		mikaeljf	5159d 11h	/versatile_mem_ctrl/trunk/syn/altera/
84		mikaeljf	5164d 10h	/versatile_mem_ctrl/trunk/syn/altera/
83		mikaeljf	5165d 05h	/versatile_mem_ctrl/trunk/syn/altera/
81		mikaeljf	5166d 06h	/versatile_mem_ctrl/trunk/syn/altera/
75		mikaeljf	5219d 04h	/versatile_mem_ctrl/trunk/syn/altera/
30	Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts.	mikaeljf	5253d 03h	/versatile_mem_ctrl/trunk/syn/altera/
22	Updated the Altera timing constraints file, also minor updates of defines file and Makefile.	mikaeljf	5272d 22h	/versatile_mem_ctrl/trunk/syn/altera/
21	Updated the Altera timing constraints file (.sdc).	mikaeljf	5277d 01h	/versatile_mem_ctrl/trunk/syn/altera/
20	Minor update of sdc-file.	mikaeljf	5279d 03h	/versatile_mem_ctrl/trunk/syn/altera/
15	Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera.	mikaeljf	5290d 04h	/versatile_mem_ctrl/trunk/syn/altera/