URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [tags/] [Rev2/] - Rev 12

Rev	Log message	Author	Age	Path
12	Minor update of whishbone FSMs in TB	mikaeljf	5376d 13h	/versatile_mem_ctrl/tags/Rev2/
11	Initial version with support for DDR	mikaeljf	5377d 00h	/versatile_mem_ctrl/tags/Rev2/
10		unneback	5404d 08h	/versatile_mem_ctrl/tags/Rev2/
9	testbench	unneback	5404d 08h	/versatile_mem_ctrl/tags/Rev2/
8		unneback	5500d 05h	/versatile_mem_ctrl/tags/Rev2/
7		unneback	5500d 05h	/versatile_mem_ctrl/tags/Rev2/
6		unneback	5500d 05h	/versatile_mem_ctrl/tags/Rev2/
5	pass initial testing	unneback	5500d 05h	/versatile_mem_ctrl/tags/Rev2/
4		unneback	5501d 08h	/versatile_mem_ctrl/tags/Rev2/
3		unneback	5501d 11h	/versatile_mem_ctrl/tags/Rev2/
2	initial	unneback	5507d 09h	/versatile_mem_ctrl/tags/Rev2/
1	The project was created and the structure was created	root	5507d 09h	/versatile_mem_ctrl/tags/Rev2/