URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [tags/] [Rev2/] [bench/] - Rev 14

Rev	Log message	Author	Age	Path
14	Added external feedback of DDR SDRAM clock.	mikaeljf	5366d 12h	/versatile_mem_ctrl/tags/Rev2/bench/
13	Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback.	mikaeljf	5366d 15h	/versatile_mem_ctrl/tags/Rev2/bench/
12	Minor update of whishbone FSMs in TB	mikaeljf	5376d 16h	/versatile_mem_ctrl/tags/Rev2/bench/
11	Initial version with support for DDR	mikaeljf	5377d 04h	/versatile_mem_ctrl/tags/Rev2/bench/
10		unneback	5404d 12h	/versatile_mem_ctrl/tags/Rev2/bench/
9	testbench	unneback	5404d 12h	/versatile_mem_ctrl/tags/Rev2/bench/