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[/] [versatile_mem_ctrl/] [tags/] [Rev2/] [rtl/] [verilog/] - Rev 109

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Rev Log message Author Age Path
109 Rev2 from trunk unneback 4723d 07h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
107 corrected signal type for ba unneback 4879d 12h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
106 added texinfo User guide and updated fsm unneback 4896d 23h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
105 versatile_mem modules naming unneback 4904d 06h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
104 versatile_mem modules naming unneback 4904d 06h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
102 cleaning up unneback 4935d 06h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
101 cleaning up unneback 4935d 06h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
100 unneback 4935d 06h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
98 updates unneback 5038d 11h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
97 updated tb and sdram16 unneback 5039d 00h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
95 new files unneback 5074d 01h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
86 mikaeljf 5145d 13h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
85 Added a versatile_mem_ctrl specific version of the flag generation module in the versatile fifo. mikaeljf 5146d 13h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
84 mikaeljf 5150d 12h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
82 mikaeljf 5151d 12h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
81 mikaeljf 5152d 08h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
80 mikaeljf 5152d 09h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
79 Added defines that fix bugs with slow wishbone clocks doing burst writes julius 5189d 23h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
78 Burst writing working again, although its mostly hardcoded to burst 4. Also added a fix for when the RAM and bus clocks are about the same speed, to avoid buffer overrun julius 5192d 06h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/
77 SDR 16 registering of current_fifo_empty signal in top, appropriate control alterations in fsm_sdr_16 julius 5200d 04h /versatile_mem_ctrl/tags/Rev2/rtl/verilog/

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