URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [tags/] [Rev2/] [sim/] [rtl_sim/] - Rev 109

Rev	Log message	Author	Age	Path
109	Rev2 from trunk	unneback	4701d 01h	/versatile_mem_ctrl/tags/Rev2/sim/rtl_sim/
86		mikaeljf	5123d 07h	/versatile_mem_ctrl/tags/Rev2/sim/rtl_sim/
82		mikaeljf	5129d 05h	/versatile_mem_ctrl/tags/Rev2/sim/rtl_sim/
80		mikaeljf	5130d 03h	/versatile_mem_ctrl/tags/Rev2/sim/rtl_sim/
75		mikaeljf	5183d 00h	/versatile_mem_ctrl/tags/Rev2/sim/rtl_sim/
70		mikaeljf	5190d 08h	/versatile_mem_ctrl/tags/Rev2/sim/rtl_sim/
69		mikaeljf	5191d 04h	/versatile_mem_ctrl/tags/Rev2/sim/rtl_sim/
31	Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts.	mikaeljf	5216d 23h	/versatile_mem_ctrl/tags/Rev2/sim/rtl_sim/
28	Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'.	mikaeljf	5221d 01h	/versatile_mem_ctrl/tags/Rev2/sim/rtl_sim/
19	Added do-file for Modelsim waveform viewer.	mikaeljf	5249d 03h	/versatile_mem_ctrl/tags/Rev2/sim/rtl_sim/
15	Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera.	mikaeljf	5254d 00h	/versatile_mem_ctrl/tags/Rev2/sim/rtl_sim/