URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] - Rev 13

Rev	Log message	Author	Age	Path
13	Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback.	mikaeljf	5321d 05h	/versatile_mem_ctrl/trunk/
12	Minor update of whishbone FSMs in TB	mikaeljf	5331d 05h	/versatile_mem_ctrl/trunk/
11	Initial version with support for DDR	mikaeljf	5331d 17h	/versatile_mem_ctrl/trunk/
10		unneback	5359d 01h	/versatile_mem_ctrl/trunk/
9	testbench	unneback	5359d 01h	/versatile_mem_ctrl/trunk/
8		unneback	5454d 21h	/versatile_mem_ctrl/trunk/
7		unneback	5454d 21h	/versatile_mem_ctrl/trunk/
6		unneback	5454d 21h	/versatile_mem_ctrl/trunk/
5	pass initial testing	unneback	5454d 22h	/versatile_mem_ctrl/trunk/
4		unneback	5456d 01h	/versatile_mem_ctrl/trunk/
3		unneback	5456d 03h	/versatile_mem_ctrl/trunk/
2	initial	unneback	5462d 01h	/versatile_mem_ctrl/trunk/
1	The project was created and the structure was created	root	5462d 02h	/versatile_mem_ctrl/trunk/