URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] - Rev 14

Rev	Log message	Author	Age	Path
14	Added external feedback of DDR SDRAM clock.	mikaeljf	5349d 09h	/versatile_mem_ctrl/trunk/
13	Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback.	mikaeljf	5349d 12h	/versatile_mem_ctrl/trunk/
12	Minor update of whishbone FSMs in TB	mikaeljf	5359d 12h	/versatile_mem_ctrl/trunk/
11	Initial version with support for DDR	mikaeljf	5360d 00h	/versatile_mem_ctrl/trunk/
10		unneback	5387d 08h	/versatile_mem_ctrl/trunk/
9	testbench	unneback	5387d 08h	/versatile_mem_ctrl/trunk/
8		unneback	5483d 04h	/versatile_mem_ctrl/trunk/
7		unneback	5483d 05h	/versatile_mem_ctrl/trunk/
6		unneback	5483d 05h	/versatile_mem_ctrl/trunk/
5	pass initial testing	unneback	5483d 05h	/versatile_mem_ctrl/trunk/
4		unneback	5484d 08h	/versatile_mem_ctrl/trunk/
3		unneback	5484d 11h	/versatile_mem_ctrl/trunk/
2	initial	unneback	5490d 09h	/versatile_mem_ctrl/trunk/
1	The project was created and the structure was created	root	5490d 09h	/versatile_mem_ctrl/trunk/