URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] - Rev 17

Rev	Log message	Author	Age	Path
17	Modified rtl Makefile and tb_defines.v	mikaeljf	5231d 07h	/versatile_mem_ctrl/trunk/
16	Added fizzim.pl	mikaeljf	5231d 08h	/versatile_mem_ctrl/trunk/
15	Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera.	mikaeljf	5232d 08h	/versatile_mem_ctrl/trunk/
14	Added external feedback of DDR SDRAM clock.	mikaeljf	5322d 10h	/versatile_mem_ctrl/trunk/
13	Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback.	mikaeljf	5322d 13h	/versatile_mem_ctrl/trunk/
12	Minor update of whishbone FSMs in TB	mikaeljf	5332d 14h	/versatile_mem_ctrl/trunk/
11	Initial version with support for DDR	mikaeljf	5333d 02h	/versatile_mem_ctrl/trunk/
10		unneback	5360d 10h	/versatile_mem_ctrl/trunk/
9	testbench	unneback	5360d 10h	/versatile_mem_ctrl/trunk/
8		unneback	5456d 06h	/versatile_mem_ctrl/trunk/
7		unneback	5456d 06h	/versatile_mem_ctrl/trunk/
6		unneback	5456d 06h	/versatile_mem_ctrl/trunk/
5	pass initial testing	unneback	5456d 07h	/versatile_mem_ctrl/trunk/
4		unneback	5457d 10h	/versatile_mem_ctrl/trunk/
3		unneback	5457d 12h	/versatile_mem_ctrl/trunk/
2	initial	unneback	5463d 10h	/versatile_mem_ctrl/trunk/
1	The project was created and the structure was created	root	5463d 10h	/versatile_mem_ctrl/trunk/