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Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] - Rev 21

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Rev Log message Author Age Path
21 Updated the Altera timing constraints file (.sdc). mikaeljf 5269d 13h /versatile_mem_ctrl/trunk/
20 Minor update of sdc-file. mikaeljf 5271d 14h /versatile_mem_ctrl/trunk/
19 Added do-file for Modelsim waveform viewer. mikaeljf 5277d 19h /versatile_mem_ctrl/trunk/
18 Updated the rtl/verilog Makefile and the bench Makefile. mikaeljf 5278d 16h /versatile_mem_ctrl/trunk/
17 Modified rtl Makefile and tb_defines.v mikaeljf 5281d 14h /versatile_mem_ctrl/trunk/
16 Added fizzim.pl mikaeljf 5281d 15h /versatile_mem_ctrl/trunk/
15 Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera. mikaeljf 5282d 15h /versatile_mem_ctrl/trunk/
14 Added external feedback of DDR SDRAM clock. mikaeljf 5372d 17h /versatile_mem_ctrl/trunk/
13 Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback. mikaeljf 5372d 20h /versatile_mem_ctrl/trunk/
12 Minor update of whishbone FSMs in TB mikaeljf 5382d 21h /versatile_mem_ctrl/trunk/
11 Initial version with support for DDR mikaeljf 5383d 09h /versatile_mem_ctrl/trunk/
10 unneback 5410d 17h /versatile_mem_ctrl/trunk/
9 testbench unneback 5410d 17h /versatile_mem_ctrl/trunk/
8 unneback 5506d 13h /versatile_mem_ctrl/trunk/
7 unneback 5506d 13h /versatile_mem_ctrl/trunk/
6 unneback 5506d 13h /versatile_mem_ctrl/trunk/
5 pass initial testing unneback 5506d 14h /versatile_mem_ctrl/trunk/
4 unneback 5507d 17h /versatile_mem_ctrl/trunk/
3 unneback 5507d 19h /versatile_mem_ctrl/trunk/
2 initial unneback 5513d 17h /versatile_mem_ctrl/trunk/

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