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URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] - Rev 27

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Rev Log message Author Age Path
27 unneback 5320d 00h /versatile_mem_ctrl/trunk/
26 compiles OK, not simulated unneback 5321d 23h /versatile_mem_ctrl/trunk/
25 unneback 5322d 02h /versatile_mem_ctrl/trunk/
24 Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions. mikaeljf 5322d 13h /versatile_mem_ctrl/trunk/
23 Removed redundant code. mikaeljf 5330d 06h /versatile_mem_ctrl/trunk/
22 Updated the Altera timing constraints file, also minor updates of defines file and Makefile. mikaeljf 5332d 02h /versatile_mem_ctrl/trunk/
21 Updated the Altera timing constraints file (.sdc). mikaeljf 5336d 05h /versatile_mem_ctrl/trunk/
20 Minor update of sdc-file. mikaeljf 5338d 06h /versatile_mem_ctrl/trunk/
19 Added do-file for Modelsim waveform viewer. mikaeljf 5344d 11h /versatile_mem_ctrl/trunk/
18 Updated the rtl/verilog Makefile and the bench Makefile. mikaeljf 5345d 08h /versatile_mem_ctrl/trunk/
17 Modified rtl Makefile and tb_defines.v mikaeljf 5348d 07h /versatile_mem_ctrl/trunk/
16 Added fizzim.pl mikaeljf 5348d 07h /versatile_mem_ctrl/trunk/
15 Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera. mikaeljf 5349d 07h /versatile_mem_ctrl/trunk/
14 Added external feedback of DDR SDRAM clock. mikaeljf 5439d 10h /versatile_mem_ctrl/trunk/
13 Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback. mikaeljf 5439d 12h /versatile_mem_ctrl/trunk/
12 Minor update of whishbone FSMs in TB mikaeljf 5449d 13h /versatile_mem_ctrl/trunk/
11 Initial version with support for DDR mikaeljf 5450d 01h /versatile_mem_ctrl/trunk/
10 unneback 5477d 09h /versatile_mem_ctrl/trunk/
9 testbench unneback 5477d 09h /versatile_mem_ctrl/trunk/
8 unneback 5573d 05h /versatile_mem_ctrl/trunk/

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