OpenCores
URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] - Rev 29

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
29 Adapted the test bench to the new wishbone interface. mikaeljf 5207d 20h /versatile_mem_ctrl/trunk/
28 Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'. mikaeljf 5207d 22h /versatile_mem_ctrl/trunk/
27 unneback 5211d 14h /versatile_mem_ctrl/trunk/
26 compiles OK, not simulated unneback 5213d 13h /versatile_mem_ctrl/trunk/
25 unneback 5213d 15h /versatile_mem_ctrl/trunk/
24 Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions. mikaeljf 5214d 03h /versatile_mem_ctrl/trunk/
23 Removed redundant code. mikaeljf 5221d 19h /versatile_mem_ctrl/trunk/
22 Updated the Altera timing constraints file, also minor updates of defines file and Makefile. mikaeljf 5223d 15h /versatile_mem_ctrl/trunk/
21 Updated the Altera timing constraints file (.sdc). mikaeljf 5227d 18h /versatile_mem_ctrl/trunk/
20 Minor update of sdc-file. mikaeljf 5229d 20h /versatile_mem_ctrl/trunk/
19 Added do-file for Modelsim waveform viewer. mikaeljf 5236d 00h /versatile_mem_ctrl/trunk/
18 Updated the rtl/verilog Makefile and the bench Makefile. mikaeljf 5236d 21h /versatile_mem_ctrl/trunk/
17 Modified rtl Makefile and tb_defines.v mikaeljf 5239d 20h /versatile_mem_ctrl/trunk/
16 Added fizzim.pl mikaeljf 5239d 21h /versatile_mem_ctrl/trunk/
15 Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera. mikaeljf 5240d 21h /versatile_mem_ctrl/trunk/
14 Added external feedback of DDR SDRAM clock. mikaeljf 5330d 23h /versatile_mem_ctrl/trunk/
13 Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback. mikaeljf 5331d 02h /versatile_mem_ctrl/trunk/
12 Minor update of whishbone FSMs in TB mikaeljf 5341d 03h /versatile_mem_ctrl/trunk/
11 Initial version with support for DDR mikaeljf 5341d 15h /versatile_mem_ctrl/trunk/
10 unneback 5368d 23h /versatile_mem_ctrl/trunk/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.