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[/] [versatile_mem_ctrl/] [trunk/] - Rev 33

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Rev Log message Author Age Path
33 work for limited test case, no cke inhibit for fifo empty unneback 5245d 05h /versatile_mem_ctrl/trunk/
32 Updated the testbench to match the new wishbone interface. mikaeljf 5248d 09h /versatile_mem_ctrl/trunk/
31 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5250d 02h /versatile_mem_ctrl/trunk/
30 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5250d 02h /versatile_mem_ctrl/trunk/
29 Adapted the test bench to the new wishbone interface. mikaeljf 5254d 02h /versatile_mem_ctrl/trunk/
28 Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'. mikaeljf 5254d 04h /versatile_mem_ctrl/trunk/
27 unneback 5257d 19h /versatile_mem_ctrl/trunk/
26 compiles OK, not simulated unneback 5259d 18h /versatile_mem_ctrl/trunk/
25 unneback 5259d 21h /versatile_mem_ctrl/trunk/
24 Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions. mikaeljf 5260d 08h /versatile_mem_ctrl/trunk/
23 Removed redundant code. mikaeljf 5268d 01h /versatile_mem_ctrl/trunk/
22 Updated the Altera timing constraints file, also minor updates of defines file and Makefile. mikaeljf 5269d 21h /versatile_mem_ctrl/trunk/
21 Updated the Altera timing constraints file (.sdc). mikaeljf 5274d 00h /versatile_mem_ctrl/trunk/
20 Minor update of sdc-file. mikaeljf 5276d 01h /versatile_mem_ctrl/trunk/
19 Added do-file for Modelsim waveform viewer. mikaeljf 5282d 06h /versatile_mem_ctrl/trunk/
18 Updated the rtl/verilog Makefile and the bench Makefile. mikaeljf 5283d 03h /versatile_mem_ctrl/trunk/
17 Modified rtl Makefile and tb_defines.v mikaeljf 5286d 02h /versatile_mem_ctrl/trunk/
16 Added fizzim.pl mikaeljf 5286d 02h /versatile_mem_ctrl/trunk/
15 Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera. mikaeljf 5287d 03h /versatile_mem_ctrl/trunk/
14 Added external feedback of DDR SDRAM clock. mikaeljf 5377d 05h /versatile_mem_ctrl/trunk/

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