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Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] - Rev 42

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Rev Log message Author Age Path
42 added pipeline stage for egress FIFO readot unneback 5269d 17h /versatile_mem_ctrl/trunk/
41 Added two alternate data capture functions. mikaeljf 5270d 01h /versatile_mem_ctrl/trunk/
40 updated fifo interfaces with re/rd and we/wr unneback 5270d 08h /versatile_mem_ctrl/trunk/
39 updated FIFO and SDR 16 unneback 5270d 19h /versatile_mem_ctrl/trunk/
38 casex in rw state to save logic unneback 5273d 03h /versatile_mem_ctrl/trunk/
37 unneback 5273d 17h /versatile_mem_ctrl/trunk/
36 unneback 5273d 18h /versatile_mem_ctrl/trunk/
35 work for limited test case unneback 5274d 01h /versatile_mem_ctrl/trunk/
34 added unneback 5274d 01h /versatile_mem_ctrl/trunk/
33 work for limited test case, no cke inhibit for fifo empty unneback 5274d 04h /versatile_mem_ctrl/trunk/
32 Updated the testbench to match the new wishbone interface. mikaeljf 5277d 07h /versatile_mem_ctrl/trunk/
31 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5279d 01h /versatile_mem_ctrl/trunk/
30 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5279d 01h /versatile_mem_ctrl/trunk/
29 Adapted the test bench to the new wishbone interface. mikaeljf 5283d 01h /versatile_mem_ctrl/trunk/
28 Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'. mikaeljf 5283d 03h /versatile_mem_ctrl/trunk/
27 unneback 5286d 18h /versatile_mem_ctrl/trunk/
26 compiles OK, not simulated unneback 5288d 17h /versatile_mem_ctrl/trunk/
25 unneback 5288d 20h /versatile_mem_ctrl/trunk/
24 Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions. mikaeljf 5289d 07h /versatile_mem_ctrl/trunk/
23 Removed redundant code. mikaeljf 5297d 00h /versatile_mem_ctrl/trunk/

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