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Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] - Rev 43

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Rev Log message Author Age Path
43 unneback 5189d 20h /versatile_mem_ctrl/trunk/
42 added pipeline stage for egress FIFO readot unneback 5190d 04h /versatile_mem_ctrl/trunk/
41 Added two alternate data capture functions. mikaeljf 5190d 11h /versatile_mem_ctrl/trunk/
40 updated fifo interfaces with re/rd and we/wr unneback 5190d 18h /versatile_mem_ctrl/trunk/
39 updated FIFO and SDR 16 unneback 5191d 06h /versatile_mem_ctrl/trunk/
38 casex in rw state to save logic unneback 5193d 13h /versatile_mem_ctrl/trunk/
37 unneback 5194d 04h /versatile_mem_ctrl/trunk/
36 unneback 5194d 04h /versatile_mem_ctrl/trunk/
35 work for limited test case unneback 5194d 12h /versatile_mem_ctrl/trunk/
34 added unneback 5194d 12h /versatile_mem_ctrl/trunk/
33 work for limited test case, no cke inhibit for fifo empty unneback 5194d 14h /versatile_mem_ctrl/trunk/
32 Updated the testbench to match the new wishbone interface. mikaeljf 5197d 18h /versatile_mem_ctrl/trunk/
31 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5199d 11h /versatile_mem_ctrl/trunk/
30 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5199d 11h /versatile_mem_ctrl/trunk/
29 Adapted the test bench to the new wishbone interface. mikaeljf 5203d 11h /versatile_mem_ctrl/trunk/
28 Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'. mikaeljf 5203d 13h /versatile_mem_ctrl/trunk/
27 unneback 5207d 05h /versatile_mem_ctrl/trunk/
26 compiles OK, not simulated unneback 5209d 04h /versatile_mem_ctrl/trunk/
25 unneback 5209d 07h /versatile_mem_ctrl/trunk/
24 Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions. mikaeljf 5209d 18h /versatile_mem_ctrl/trunk/

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