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URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] - Rev 48

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Rev Log message Author Age Path
48 dq_oe fix unneback 5226d 22h /versatile_mem_ctrl/trunk/
47 support for registered outputs on ras, cas and we unneback 5226d 23h /versatile_mem_ctrl/trunk/
46 cosmetic updates unneback 5227d 00h /versatile_mem_ctrl/trunk/
45 added unneback 5227d 02h /versatile_mem_ctrl/trunk/
44 registered row comparison unneback 5229d 02h /versatile_mem_ctrl/trunk/
43 unneback 5229d 07h /versatile_mem_ctrl/trunk/
42 added pipeline stage for egress FIFO readot unneback 5229d 15h /versatile_mem_ctrl/trunk/
41 Added two alternate data capture functions. mikaeljf 5229d 23h /versatile_mem_ctrl/trunk/
40 updated fifo interfaces with re/rd and we/wr unneback 5230d 06h /versatile_mem_ctrl/trunk/
39 updated FIFO and SDR 16 unneback 5230d 17h /versatile_mem_ctrl/trunk/
38 casex in rw state to save logic unneback 5233d 01h /versatile_mem_ctrl/trunk/
37 unneback 5233d 15h /versatile_mem_ctrl/trunk/
36 unneback 5233d 16h /versatile_mem_ctrl/trunk/
35 work for limited test case unneback 5233d 23h /versatile_mem_ctrl/trunk/
34 added unneback 5233d 23h /versatile_mem_ctrl/trunk/
33 work for limited test case, no cke inhibit for fifo empty unneback 5234d 02h /versatile_mem_ctrl/trunk/
32 Updated the testbench to match the new wishbone interface. mikaeljf 5237d 06h /versatile_mem_ctrl/trunk/
31 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5238d 23h /versatile_mem_ctrl/trunk/
30 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5238d 23h /versatile_mem_ctrl/trunk/
29 Adapted the test bench to the new wishbone interface. mikaeljf 5242d 23h /versatile_mem_ctrl/trunk/

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