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URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] - Rev 51

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Rev Log message Author Age Path
51 act exit for read updated unneback 5220d 05h /versatile_mem_ctrl/trunk/
50 Fixed up make file - THIS MAY BREAK THINGS, but it's a lot neater and easier to use, also dependencies are now properly configured, and we don't remake things unecessarily julius 5220d 07h /versatile_mem_ctrl/trunk/
49 Added versatile_fifo_dual_port_ram_dc_sw.v rule to makefile, getting it from versatile fifo project julius 5220d 09h /versatile_mem_ctrl/trunk/
48 dq_oe fix unneback 5220d 09h /versatile_mem_ctrl/trunk/
47 support for registered outputs on ras, cas and we unneback 5220d 09h /versatile_mem_ctrl/trunk/
46 cosmetic updates unneback 5220d 10h /versatile_mem_ctrl/trunk/
45 added unneback 5220d 13h /versatile_mem_ctrl/trunk/
44 registered row comparison unneback 5222d 12h /versatile_mem_ctrl/trunk/
43 unneback 5222d 18h /versatile_mem_ctrl/trunk/
42 added pipeline stage for egress FIFO readot unneback 5223d 02h /versatile_mem_ctrl/trunk/
41 Added two alternate data capture functions. mikaeljf 5223d 09h /versatile_mem_ctrl/trunk/
40 updated fifo interfaces with re/rd and we/wr unneback 5223d 16h /versatile_mem_ctrl/trunk/
39 updated FIFO and SDR 16 unneback 5224d 04h /versatile_mem_ctrl/trunk/
38 casex in rw state to save logic unneback 5226d 11h /versatile_mem_ctrl/trunk/
37 unneback 5227d 02h /versatile_mem_ctrl/trunk/
36 unneback 5227d 02h /versatile_mem_ctrl/trunk/
35 work for limited test case unneback 5227d 10h /versatile_mem_ctrl/trunk/
34 added unneback 5227d 10h /versatile_mem_ctrl/trunk/
33 work for limited test case, no cke inhibit for fifo empty unneback 5227d 12h /versatile_mem_ctrl/trunk/
32 Updated the testbench to match the new wishbone interface. mikaeljf 5230d 16h /versatile_mem_ctrl/trunk/

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