URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [bench/] - Rev 14

Rev	Log message	Author	Age	Path
14	Added external feedback of DDR SDRAM clock.	mikaeljf	5361d 13h	/versatile_mem_ctrl/trunk/bench/
13	Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback.	mikaeljf	5361d 16h	/versatile_mem_ctrl/trunk/bench/
12	Minor update of whishbone FSMs in TB	mikaeljf	5371d 17h	/versatile_mem_ctrl/trunk/bench/
11	Initial version with support for DDR	mikaeljf	5372d 05h	/versatile_mem_ctrl/trunk/bench/
10		unneback	5399d 13h	/versatile_mem_ctrl/trunk/bench/
9	testbench	unneback	5399d 13h	/versatile_mem_ctrl/trunk/bench/