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[/] [versatile_mem_ctrl/] [trunk/] [bench/] - Rev 21

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Rev Log message Author Age Path
18 Updated the rtl/verilog Makefile and the bench Makefile. mikaeljf 5382d 18h /versatile_mem_ctrl/trunk/bench/
17 Modified rtl Makefile and tb_defines.v mikaeljf 5385d 17h /versatile_mem_ctrl/trunk/bench/
15 Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera. mikaeljf 5386d 18h /versatile_mem_ctrl/trunk/bench/
14 Added external feedback of DDR SDRAM clock. mikaeljf 5476d 20h /versatile_mem_ctrl/trunk/bench/
13 Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback. mikaeljf 5476d 23h /versatile_mem_ctrl/trunk/bench/
12 Minor update of whishbone FSMs in TB mikaeljf 5487d 00h /versatile_mem_ctrl/trunk/bench/
11 Initial version with support for DDR mikaeljf 5487d 12h /versatile_mem_ctrl/trunk/bench/
10 unneback 5514d 20h /versatile_mem_ctrl/trunk/bench/
9 testbench unneback 5514d 20h /versatile_mem_ctrl/trunk/bench/

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