OpenCores
URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [bench/] - Rev 33

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
33 work for limited test case, no cke inhibit for fifo empty unneback 5194d 19h /versatile_mem_ctrl/trunk/bench/
32 Updated the testbench to match the new wishbone interface. mikaeljf 5197d 23h /versatile_mem_ctrl/trunk/bench/
29 Adapted the test bench to the new wishbone interface. mikaeljf 5203d 16h /versatile_mem_ctrl/trunk/bench/
28 Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'. mikaeljf 5203d 18h /versatile_mem_ctrl/trunk/bench/
18 Updated the rtl/verilog Makefile and the bench Makefile. mikaeljf 5232d 17h /versatile_mem_ctrl/trunk/bench/
17 Modified rtl Makefile and tb_defines.v mikaeljf 5235d 16h /versatile_mem_ctrl/trunk/bench/
15 Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera. mikaeljf 5236d 17h /versatile_mem_ctrl/trunk/bench/
14 Added external feedback of DDR SDRAM clock. mikaeljf 5326d 19h /versatile_mem_ctrl/trunk/bench/
13 Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback. mikaeljf 5326d 22h /versatile_mem_ctrl/trunk/bench/
12 Minor update of whishbone FSMs in TB mikaeljf 5336d 23h /versatile_mem_ctrl/trunk/bench/
11 Initial version with support for DDR mikaeljf 5337d 10h /versatile_mem_ctrl/trunk/bench/
10 unneback 5364d 18h /versatile_mem_ctrl/trunk/bench/
9 testbench unneback 5364d 18h /versatile_mem_ctrl/trunk/bench/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.