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[/] [versatile_mem_ctrl/] [trunk/] [bench/] - Rev 33

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Rev Log message Author Age Path
33 work for limited test case, no cke inhibit for fifo empty unneback 5234d 07h /versatile_mem_ctrl/trunk/bench/
32 Updated the testbench to match the new wishbone interface. mikaeljf 5237d 11h /versatile_mem_ctrl/trunk/bench/
29 Adapted the test bench to the new wishbone interface. mikaeljf 5243d 04h /versatile_mem_ctrl/trunk/bench/
28 Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'. mikaeljf 5243d 06h /versatile_mem_ctrl/trunk/bench/
18 Updated the rtl/verilog Makefile and the bench Makefile. mikaeljf 5272d 06h /versatile_mem_ctrl/trunk/bench/
17 Modified rtl Makefile and tb_defines.v mikaeljf 5275d 04h /versatile_mem_ctrl/trunk/bench/
15 Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera. mikaeljf 5276d 05h /versatile_mem_ctrl/trunk/bench/
14 Added external feedback of DDR SDRAM clock. mikaeljf 5366d 07h /versatile_mem_ctrl/trunk/bench/
13 Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback. mikaeljf 5366d 10h /versatile_mem_ctrl/trunk/bench/
12 Minor update of whishbone FSMs in TB mikaeljf 5376d 11h /versatile_mem_ctrl/trunk/bench/
11 Initial version with support for DDR mikaeljf 5376d 23h /versatile_mem_ctrl/trunk/bench/
10 unneback 5404d 07h /versatile_mem_ctrl/trunk/bench/
9 testbench unneback 5404d 07h /versatile_mem_ctrl/trunk/bench/

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