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URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [rtl/] - Rev 108

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Rev Log message Author Age Path
107 corrected signal type for ba unneback 4840d 01h /versatile_mem_ctrl/trunk/rtl/
106 added texinfo User guide and updated fsm unneback 4857d 12h /versatile_mem_ctrl/trunk/rtl/
105 versatile_mem modules naming unneback 4864d 19h /versatile_mem_ctrl/trunk/rtl/
104 versatile_mem modules naming unneback 4864d 19h /versatile_mem_ctrl/trunk/rtl/
102 cleaning up unneback 4895d 19h /versatile_mem_ctrl/trunk/rtl/
101 cleaning up unneback 4895d 19h /versatile_mem_ctrl/trunk/rtl/
100 unneback 4895d 19h /versatile_mem_ctrl/trunk/rtl/
98 updates unneback 4999d 00h /versatile_mem_ctrl/trunk/rtl/
97 updated tb and sdram16 unneback 4999d 13h /versatile_mem_ctrl/trunk/rtl/
95 new files unneback 5034d 14h /versatile_mem_ctrl/trunk/rtl/
86 mikaeljf 5106d 02h /versatile_mem_ctrl/trunk/rtl/
85 Added a versatile_mem_ctrl specific version of the flag generation module in the versatile fifo. mikaeljf 5107d 02h /versatile_mem_ctrl/trunk/rtl/
84 mikaeljf 5111d 01h /versatile_mem_ctrl/trunk/rtl/
82 mikaeljf 5112d 01h /versatile_mem_ctrl/trunk/rtl/
81 mikaeljf 5112d 21h /versatile_mem_ctrl/trunk/rtl/
80 mikaeljf 5112d 22h /versatile_mem_ctrl/trunk/rtl/
79 Added defines that fix bugs with slow wishbone clocks doing burst writes julius 5150d 12h /versatile_mem_ctrl/trunk/rtl/
78 Burst writing working again, although its mostly hardcoded to burst 4. Also added a fix for when the RAM and bus clocks are about the same speed, to avoid buffer overrun julius 5152d 19h /versatile_mem_ctrl/trunk/rtl/
77 SDR 16 registering of current_fifo_empty signal in top, appropriate control alterations in fsm_sdr_16 julius 5160d 17h /versatile_mem_ctrl/trunk/rtl/
76 Changed SDR16 synthesis useioff location, fsm_wb acking logic, default SDR build is for 16m part now julius 5165d 18h /versatile_mem_ctrl/trunk/rtl/

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