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[/] [versatile_mem_ctrl/] [trunk/] [rtl/] - Rev 17

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Rev Log message Author Age Path
17 Modified rtl Makefile and tb_defines.v mikaeljf 5240d 15h /versatile_mem_ctrl/trunk/rtl/
16 Added fizzim.pl mikaeljf 5240d 16h /versatile_mem_ctrl/trunk/rtl/
15 Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera. mikaeljf 5241d 16h /versatile_mem_ctrl/trunk/rtl/
13 Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback. mikaeljf 5331d 21h /versatile_mem_ctrl/trunk/rtl/
11 Initial version with support for DDR mikaeljf 5342d 10h /versatile_mem_ctrl/trunk/rtl/
7 unneback 5465d 14h /versatile_mem_ctrl/trunk/rtl/
6 unneback 5465d 14h /versatile_mem_ctrl/trunk/rtl/
5 pass initial testing unneback 5465d 15h /versatile_mem_ctrl/trunk/rtl/
4 unneback 5466d 17h /versatile_mem_ctrl/trunk/rtl/
3 unneback 5466d 20h /versatile_mem_ctrl/trunk/rtl/
2 initial unneback 5472d 18h /versatile_mem_ctrl/trunk/rtl/

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