URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [rtl/] - Rev 21

Rev	Log message	Author	Age	Path
21	Updated the Altera timing constraints file (.sdc).	mikaeljf	5249d 22h	/versatile_mem_ctrl/trunk/rtl/
20	Minor update of sdc-file.	mikaeljf	5251d 23h	/versatile_mem_ctrl/trunk/rtl/
19	Added do-file for Modelsim waveform viewer.	mikaeljf	5258d 04h	/versatile_mem_ctrl/trunk/rtl/
18	Updated the rtl/verilog Makefile and the bench Makefile.	mikaeljf	5259d 01h	/versatile_mem_ctrl/trunk/rtl/
17	Modified rtl Makefile and tb_defines.v	mikaeljf	5262d 00h	/versatile_mem_ctrl/trunk/rtl/
16	Added fizzim.pl	mikaeljf	5262d 00h	/versatile_mem_ctrl/trunk/rtl/
15	Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera.	mikaeljf	5263d 00h	/versatile_mem_ctrl/trunk/rtl/
13	Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback.	mikaeljf	5353d 06h	/versatile_mem_ctrl/trunk/rtl/
11	Initial version with support for DDR	mikaeljf	5363d 18h	/versatile_mem_ctrl/trunk/rtl/
7		unneback	5486d 23h	/versatile_mem_ctrl/trunk/rtl/
6		unneback	5486d 23h	/versatile_mem_ctrl/trunk/rtl/
5	pass initial testing	unneback	5486d 23h	/versatile_mem_ctrl/trunk/rtl/
4		unneback	5488d 02h	/versatile_mem_ctrl/trunk/rtl/
3		unneback	5488d 05h	/versatile_mem_ctrl/trunk/rtl/
2	initial	unneback	5494d 03h	/versatile_mem_ctrl/trunk/rtl/