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[/] [versatile_mem_ctrl/] [trunk/] [rtl/] - Rev 22

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Rev Log message Author Age Path
22 Updated the Altera timing constraints file, also minor updates of defines file and Makefile. mikaeljf 5219d 14h /versatile_mem_ctrl/trunk/rtl/
21 Updated the Altera timing constraints file (.sdc). mikaeljf 5223d 18h /versatile_mem_ctrl/trunk/rtl/
20 Minor update of sdc-file. mikaeljf 5225d 19h /versatile_mem_ctrl/trunk/rtl/
19 Added do-file for Modelsim waveform viewer. mikaeljf 5232d 00h /versatile_mem_ctrl/trunk/rtl/
18 Updated the rtl/verilog Makefile and the bench Makefile. mikaeljf 5232d 21h /versatile_mem_ctrl/trunk/rtl/
17 Modified rtl Makefile and tb_defines.v mikaeljf 5235d 20h /versatile_mem_ctrl/trunk/rtl/
16 Added fizzim.pl mikaeljf 5235d 20h /versatile_mem_ctrl/trunk/rtl/
15 Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera. mikaeljf 5236d 20h /versatile_mem_ctrl/trunk/rtl/
13 Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback. mikaeljf 5327d 01h /versatile_mem_ctrl/trunk/rtl/
11 Initial version with support for DDR mikaeljf 5337d 14h /versatile_mem_ctrl/trunk/rtl/
7 unneback 5460d 18h /versatile_mem_ctrl/trunk/rtl/
6 unneback 5460d 18h /versatile_mem_ctrl/trunk/rtl/
5 pass initial testing unneback 5460d 19h /versatile_mem_ctrl/trunk/rtl/
4 unneback 5461d 22h /versatile_mem_ctrl/trunk/rtl/
3 unneback 5462d 00h /versatile_mem_ctrl/trunk/rtl/
2 initial unneback 5467d 22h /versatile_mem_ctrl/trunk/rtl/

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