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[/] [versatile_mem_ctrl/] [trunk/] [rtl/] - Rev 35

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Rev Log message Author Age Path
35 work for limited test case unneback 5194d 14h /versatile_mem_ctrl/trunk/rtl/
34 added unneback 5194d 14h /versatile_mem_ctrl/trunk/rtl/
33 work for limited test case, no cke inhibit for fifo empty unneback 5194d 16h /versatile_mem_ctrl/trunk/rtl/
32 Updated the testbench to match the new wishbone interface. mikaeljf 5197d 20h /versatile_mem_ctrl/trunk/rtl/
31 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5199d 13h /versatile_mem_ctrl/trunk/rtl/
30 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5199d 13h /versatile_mem_ctrl/trunk/rtl/
28 Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'. mikaeljf 5203d 15h /versatile_mem_ctrl/trunk/rtl/
27 unneback 5207d 07h /versatile_mem_ctrl/trunk/rtl/
26 compiles OK, not simulated unneback 5209d 06h /versatile_mem_ctrl/trunk/rtl/
25 unneback 5209d 09h /versatile_mem_ctrl/trunk/rtl/
24 Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions. mikaeljf 5209d 20h /versatile_mem_ctrl/trunk/rtl/
23 Removed redundant code. mikaeljf 5217d 13h /versatile_mem_ctrl/trunk/rtl/
22 Updated the Altera timing constraints file, also minor updates of defines file and Makefile. mikaeljf 5219d 08h /versatile_mem_ctrl/trunk/rtl/
21 Updated the Altera timing constraints file (.sdc). mikaeljf 5223d 12h /versatile_mem_ctrl/trunk/rtl/
20 Minor update of sdc-file. mikaeljf 5225d 13h /versatile_mem_ctrl/trunk/rtl/
19 Added do-file for Modelsim waveform viewer. mikaeljf 5231d 18h /versatile_mem_ctrl/trunk/rtl/
18 Updated the rtl/verilog Makefile and the bench Makefile. mikaeljf 5232d 15h /versatile_mem_ctrl/trunk/rtl/
17 Modified rtl Makefile and tb_defines.v mikaeljf 5235d 14h /versatile_mem_ctrl/trunk/rtl/
16 Added fizzim.pl mikaeljf 5235d 14h /versatile_mem_ctrl/trunk/rtl/
15 Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera. mikaeljf 5236d 14h /versatile_mem_ctrl/trunk/rtl/

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