URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [rtl/] - Rev 43

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Rev	Log message	Author	Age	Path
42	added pipeline stage for egress FIFO readot	unneback	5190d 12h	/versatile_mem_ctrl/trunk/rtl/
41	Added two alternate data capture functions.	mikaeljf	5190d 20h	/versatile_mem_ctrl/trunk/rtl/
40	updated fifo interfaces with re/rd and we/wr	unneback	5191d 03h	/versatile_mem_ctrl/trunk/rtl/
39	updated FIFO and SDR 16	unneback	5191d 14h	/versatile_mem_ctrl/trunk/rtl/
38	casex in rw state to save logic	unneback	5193d 22h	/versatile_mem_ctrl/trunk/rtl/
37		unneback	5194d 12h	/versatile_mem_ctrl/trunk/rtl/
36		unneback	5194d 13h	/versatile_mem_ctrl/trunk/rtl/
35	work for limited test case	unneback	5194d 20h	/versatile_mem_ctrl/trunk/rtl/
34	added	unneback	5194d 20h	/versatile_mem_ctrl/trunk/rtl/
33	work for limited test case, no cke inhibit for fifo empty	unneback	5194d 23h	/versatile_mem_ctrl/trunk/rtl/
32	Updated the testbench to match the new wishbone interface.	mikaeljf	5198d 03h	/versatile_mem_ctrl/trunk/rtl/
31	Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts.	mikaeljf	5199d 20h	/versatile_mem_ctrl/trunk/rtl/
30	Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts.	mikaeljf	5199d 20h	/versatile_mem_ctrl/trunk/rtl/
28	Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'.	mikaeljf	5203d 22h	/versatile_mem_ctrl/trunk/rtl/
27		unneback	5207d 13h	/versatile_mem_ctrl/trunk/rtl/
26	compiles OK, not simulated	unneback	5209d 12h	/versatile_mem_ctrl/trunk/rtl/
25		unneback	5209d 15h	/versatile_mem_ctrl/trunk/rtl/
24	Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions.	mikaeljf	5210d 02h	/versatile_mem_ctrl/trunk/rtl/
23	Removed redundant code.	mikaeljf	5217d 19h	/versatile_mem_ctrl/trunk/rtl/
22	Updated the Altera timing constraints file, also minor updates of defines file and Makefile.	mikaeljf	5219d 15h	/versatile_mem_ctrl/trunk/rtl/

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Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [rtl/] - Rev 43

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