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Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [rtl/] - Rev 46

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Rev Log message Author Age Path
46 cosmetic updates unneback 5256d 15h /versatile_mem_ctrl/trunk/rtl/
45 added unneback 5256d 17h /versatile_mem_ctrl/trunk/rtl/
44 registered row comparison unneback 5258d 17h /versatile_mem_ctrl/trunk/rtl/
42 added pipeline stage for egress FIFO readot unneback 5259d 06h /versatile_mem_ctrl/trunk/rtl/
41 Added two alternate data capture functions. mikaeljf 5259d 14h /versatile_mem_ctrl/trunk/rtl/
40 updated fifo interfaces with re/rd and we/wr unneback 5259d 21h /versatile_mem_ctrl/trunk/rtl/
39 updated FIFO and SDR 16 unneback 5260d 09h /versatile_mem_ctrl/trunk/rtl/
38 casex in rw state to save logic unneback 5262d 16h /versatile_mem_ctrl/trunk/rtl/
37 unneback 5263d 07h /versatile_mem_ctrl/trunk/rtl/
36 unneback 5263d 07h /versatile_mem_ctrl/trunk/rtl/
35 work for limited test case unneback 5263d 14h /versatile_mem_ctrl/trunk/rtl/
34 added unneback 5263d 15h /versatile_mem_ctrl/trunk/rtl/
33 work for limited test case, no cke inhibit for fifo empty unneback 5263d 17h /versatile_mem_ctrl/trunk/rtl/
32 Updated the testbench to match the new wishbone interface. mikaeljf 5266d 21h /versatile_mem_ctrl/trunk/rtl/
31 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5268d 14h /versatile_mem_ctrl/trunk/rtl/
30 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5268d 14h /versatile_mem_ctrl/trunk/rtl/
28 Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'. mikaeljf 5272d 16h /versatile_mem_ctrl/trunk/rtl/
27 unneback 5276d 07h /versatile_mem_ctrl/trunk/rtl/
26 compiles OK, not simulated unneback 5278d 07h /versatile_mem_ctrl/trunk/rtl/
25 unneback 5278d 09h /versatile_mem_ctrl/trunk/rtl/

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