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[/] [versatile_mem_ctrl/] [trunk/] [rtl/] - Rev 52

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Rev Log message Author Age Path
52 act exit for read updated unneback 5256d 10h /versatile_mem_ctrl/trunk/rtl/
51 act exit for read updated unneback 5256d 10h /versatile_mem_ctrl/trunk/rtl/
50 Fixed up make file - THIS MAY BREAK THINGS, but it's a lot neater and easier to use, also dependencies are now properly configured, and we don't remake things unecessarily julius 5256d 12h /versatile_mem_ctrl/trunk/rtl/
49 Added versatile_fifo_dual_port_ram_dc_sw.v rule to makefile, getting it from versatile fifo project julius 5256d 14h /versatile_mem_ctrl/trunk/rtl/
48 dq_oe fix unneback 5256d 14h /versatile_mem_ctrl/trunk/rtl/
47 support for registered outputs on ras, cas and we unneback 5256d 15h /versatile_mem_ctrl/trunk/rtl/
46 cosmetic updates unneback 5256d 15h /versatile_mem_ctrl/trunk/rtl/
45 added unneback 5256d 18h /versatile_mem_ctrl/trunk/rtl/
44 registered row comparison unneback 5258d 18h /versatile_mem_ctrl/trunk/rtl/
42 added pipeline stage for egress FIFO readot unneback 5259d 07h /versatile_mem_ctrl/trunk/rtl/
41 Added two alternate data capture functions. mikaeljf 5259d 15h /versatile_mem_ctrl/trunk/rtl/
40 updated fifo interfaces with re/rd and we/wr unneback 5259d 22h /versatile_mem_ctrl/trunk/rtl/
39 updated FIFO and SDR 16 unneback 5260d 09h /versatile_mem_ctrl/trunk/rtl/
38 casex in rw state to save logic unneback 5262d 17h /versatile_mem_ctrl/trunk/rtl/
37 unneback 5263d 07h /versatile_mem_ctrl/trunk/rtl/
36 unneback 5263d 08h /versatile_mem_ctrl/trunk/rtl/
35 work for limited test case unneback 5263d 15h /versatile_mem_ctrl/trunk/rtl/
34 added unneback 5263d 15h /versatile_mem_ctrl/trunk/rtl/
33 work for limited test case, no cke inhibit for fifo empty unneback 5263d 18h /versatile_mem_ctrl/trunk/rtl/
32 Updated the testbench to match the new wishbone interface. mikaeljf 5266d 21h /versatile_mem_ctrl/trunk/rtl/

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