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[/] [versatile_mem_ctrl/] [trunk/] [rtl/] - Rev 58

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Rev Log message Author Age Path
58 sdr_16 fixes for timing - extra egress register stage, appropriate changes in sdr_16 fsm julius 5236d 12h /versatile_mem_ctrl/trunk/rtl/
57 added support for early termination of burst access unneback 5237d 14h /versatile_mem_ctrl/trunk/rtl/
56 corrected fifo_rd_data in state w4d unneback 5239d 07h /versatile_mem_ctrl/trunk/rtl/
55 Fixed up sdr16 dqm output julius 5240d 02h /versatile_mem_ctrl/trunk/rtl/
54 dqm moved into FSM unneback 5240d 23h /versatile_mem_ctrl/trunk/rtl/
53 unneback 5240d 23h /versatile_mem_ctrl/trunk/rtl/
52 act exit for read updated unneback 5242d 00h /versatile_mem_ctrl/trunk/rtl/
51 act exit for read updated unneback 5242d 00h /versatile_mem_ctrl/trunk/rtl/
50 Fixed up make file - THIS MAY BREAK THINGS, but it's a lot neater and easier to use, also dependencies are now properly configured, and we don't remake things unecessarily julius 5242d 03h /versatile_mem_ctrl/trunk/rtl/
49 Added versatile_fifo_dual_port_ram_dc_sw.v rule to makefile, getting it from versatile fifo project julius 5242d 04h /versatile_mem_ctrl/trunk/rtl/
48 dq_oe fix unneback 5242d 04h /versatile_mem_ctrl/trunk/rtl/
47 support for registered outputs on ras, cas and we unneback 5242d 05h /versatile_mem_ctrl/trunk/rtl/
46 cosmetic updates unneback 5242d 06h /versatile_mem_ctrl/trunk/rtl/
45 added unneback 5242d 08h /versatile_mem_ctrl/trunk/rtl/
44 registered row comparison unneback 5244d 08h /versatile_mem_ctrl/trunk/rtl/
42 added pipeline stage for egress FIFO readot unneback 5244d 21h /versatile_mem_ctrl/trunk/rtl/
41 Added two alternate data capture functions. mikaeljf 5245d 05h /versatile_mem_ctrl/trunk/rtl/
40 updated fifo interfaces with re/rd and we/wr unneback 5245d 12h /versatile_mem_ctrl/trunk/rtl/
39 updated FIFO and SDR 16 unneback 5246d 00h /versatile_mem_ctrl/trunk/rtl/
38 casex in rw state to save logic unneback 5248d 07h /versatile_mem_ctrl/trunk/rtl/

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