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Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [rtl/] [verilog/] - Rev 104

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Rev Log message Author Age Path
104 versatile_mem modules naming unneback 4872d 00h /versatile_mem_ctrl/trunk/rtl/verilog/
102 cleaning up unneback 4903d 00h /versatile_mem_ctrl/trunk/rtl/verilog/
101 cleaning up unneback 4903d 00h /versatile_mem_ctrl/trunk/rtl/verilog/
100 unneback 4903d 00h /versatile_mem_ctrl/trunk/rtl/verilog/
98 updates unneback 5006d 05h /versatile_mem_ctrl/trunk/rtl/verilog/
97 updated tb and sdram16 unneback 5006d 18h /versatile_mem_ctrl/trunk/rtl/verilog/
95 new files unneback 5041d 19h /versatile_mem_ctrl/trunk/rtl/verilog/
86 mikaeljf 5113d 07h /versatile_mem_ctrl/trunk/rtl/verilog/
85 Added a versatile_mem_ctrl specific version of the flag generation module in the versatile fifo. mikaeljf 5114d 07h /versatile_mem_ctrl/trunk/rtl/verilog/
84 mikaeljf 5118d 06h /versatile_mem_ctrl/trunk/rtl/verilog/
82 mikaeljf 5119d 06h /versatile_mem_ctrl/trunk/rtl/verilog/
81 mikaeljf 5120d 02h /versatile_mem_ctrl/trunk/rtl/verilog/
80 mikaeljf 5120d 03h /versatile_mem_ctrl/trunk/rtl/verilog/
79 Added defines that fix bugs with slow wishbone clocks doing burst writes julius 5157d 17h /versatile_mem_ctrl/trunk/rtl/verilog/
78 Burst writing working again, although its mostly hardcoded to burst 4. Also added a fix for when the RAM and bus clocks are about the same speed, to avoid buffer overrun julius 5160d 00h /versatile_mem_ctrl/trunk/rtl/verilog/
77 SDR 16 registering of current_fifo_empty signal in top, appropriate control alterations in fsm_sdr_16 julius 5167d 23h /versatile_mem_ctrl/trunk/rtl/verilog/
76 Changed SDR16 synthesis useioff location, fsm_wb acking logic, default SDR build is for 16m part now julius 5173d 00h /versatile_mem_ctrl/trunk/rtl/verilog/
75 mikaeljf 5173d 01h /versatile_mem_ctrl/trunk/rtl/verilog/
74 Minor update of rtl Makefile. mikaeljf 5177d 00h /versatile_mem_ctrl/trunk/rtl/verilog/
73 Minor updates to fix lost revisions 69 and 70. mikaeljf 5177d 01h /versatile_mem_ctrl/trunk/rtl/verilog/

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