OpenCores
URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [rtl/] [verilog/] - Rev 107

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
107 corrected signal type for ba unneback 5000d 12h /versatile_mem_ctrl/trunk/rtl/verilog/
106 added texinfo User guide and updated fsm unneback 5017d 23h /versatile_mem_ctrl/trunk/rtl/verilog/
105 versatile_mem modules naming unneback 5025d 06h /versatile_mem_ctrl/trunk/rtl/verilog/
104 versatile_mem modules naming unneback 5025d 06h /versatile_mem_ctrl/trunk/rtl/verilog/
102 cleaning up unneback 5056d 06h /versatile_mem_ctrl/trunk/rtl/verilog/
101 cleaning up unneback 5056d 06h /versatile_mem_ctrl/trunk/rtl/verilog/
100 unneback 5056d 06h /versatile_mem_ctrl/trunk/rtl/verilog/
98 updates unneback 5159d 11h /versatile_mem_ctrl/trunk/rtl/verilog/
97 updated tb and sdram16 unneback 5160d 00h /versatile_mem_ctrl/trunk/rtl/verilog/
95 new files unneback 5195d 01h /versatile_mem_ctrl/trunk/rtl/verilog/
86 mikaeljf 5266d 13h /versatile_mem_ctrl/trunk/rtl/verilog/
85 Added a versatile_mem_ctrl specific version of the flag generation module in the versatile fifo. mikaeljf 5267d 13h /versatile_mem_ctrl/trunk/rtl/verilog/
84 mikaeljf 5271d 12h /versatile_mem_ctrl/trunk/rtl/verilog/
82 mikaeljf 5272d 12h /versatile_mem_ctrl/trunk/rtl/verilog/
81 mikaeljf 5273d 08h /versatile_mem_ctrl/trunk/rtl/verilog/
80 mikaeljf 5273d 09h /versatile_mem_ctrl/trunk/rtl/verilog/
79 Added defines that fix bugs with slow wishbone clocks doing burst writes julius 5310d 23h /versatile_mem_ctrl/trunk/rtl/verilog/
78 Burst writing working again, although its mostly hardcoded to burst 4. Also added a fix for when the RAM and bus clocks are about the same speed, to avoid buffer overrun julius 5313d 06h /versatile_mem_ctrl/trunk/rtl/verilog/
77 SDR 16 registering of current_fifo_empty signal in top, appropriate control alterations in fsm_sdr_16 julius 5321d 04h /versatile_mem_ctrl/trunk/rtl/verilog/
76 Changed SDR16 synthesis useioff location, fsm_wb acking logic, default SDR build is for 16m part now julius 5326d 05h /versatile_mem_ctrl/trunk/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.