URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [rtl/] [verilog/] - Rev 17

Rev	Log message	Author	Age	Path
17	Modified rtl Makefile and tb_defines.v	mikaeljf	5261d 18h	/versatile_mem_ctrl/trunk/rtl/verilog/
16	Added fizzim.pl	mikaeljf	5261d 18h	/versatile_mem_ctrl/trunk/rtl/verilog/
15	Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera.	mikaeljf	5262d 18h	/versatile_mem_ctrl/trunk/rtl/verilog/
13	Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback.	mikaeljf	5353d 00h	/versatile_mem_ctrl/trunk/rtl/verilog/
11	Initial version with support for DDR	mikaeljf	5363d 12h	/versatile_mem_ctrl/trunk/rtl/verilog/
7		unneback	5486d 16h	/versatile_mem_ctrl/trunk/rtl/verilog/
6		unneback	5486d 17h	/versatile_mem_ctrl/trunk/rtl/verilog/
5	pass initial testing	unneback	5486d 17h	/versatile_mem_ctrl/trunk/rtl/verilog/
4		unneback	5487d 20h	/versatile_mem_ctrl/trunk/rtl/verilog/
3		unneback	5487d 23h	/versatile_mem_ctrl/trunk/rtl/verilog/
2	initial	unneback	5493d 21h	/versatile_mem_ctrl/trunk/rtl/verilog/