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[/] [versatile_mem_ctrl/] [trunk/] [rtl/] [verilog/] - Rev 25

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Rev Log message Author Age Path
25 unneback 5228d 22h /versatile_mem_ctrl/trunk/rtl/verilog/
24 Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions. mikaeljf 5229d 09h /versatile_mem_ctrl/trunk/rtl/verilog/
23 Removed redundant code. mikaeljf 5237d 02h /versatile_mem_ctrl/trunk/rtl/verilog/
22 Updated the Altera timing constraints file, also minor updates of defines file and Makefile. mikaeljf 5238d 22h /versatile_mem_ctrl/trunk/rtl/verilog/
21 Updated the Altera timing constraints file (.sdc). mikaeljf 5243d 01h /versatile_mem_ctrl/trunk/rtl/verilog/
20 Minor update of sdc-file. mikaeljf 5245d 03h /versatile_mem_ctrl/trunk/rtl/verilog/
19 Added do-file for Modelsim waveform viewer. mikaeljf 5251d 07h /versatile_mem_ctrl/trunk/rtl/verilog/
18 Updated the rtl/verilog Makefile and the bench Makefile. mikaeljf 5252d 04h /versatile_mem_ctrl/trunk/rtl/verilog/
17 Modified rtl Makefile and tb_defines.v mikaeljf 5255d 03h /versatile_mem_ctrl/trunk/rtl/verilog/
16 Added fizzim.pl mikaeljf 5255d 04h /versatile_mem_ctrl/trunk/rtl/verilog/
15 Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera. mikaeljf 5256d 04h /versatile_mem_ctrl/trunk/rtl/verilog/
13 Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback. mikaeljf 5346d 09h /versatile_mem_ctrl/trunk/rtl/verilog/
11 Initial version with support for DDR mikaeljf 5356d 21h /versatile_mem_ctrl/trunk/rtl/verilog/
7 unneback 5480d 02h /versatile_mem_ctrl/trunk/rtl/verilog/
6 unneback 5480d 02h /versatile_mem_ctrl/trunk/rtl/verilog/
5 pass initial testing unneback 5480d 02h /versatile_mem_ctrl/trunk/rtl/verilog/
4 unneback 5481d 05h /versatile_mem_ctrl/trunk/rtl/verilog/
3 unneback 5481d 08h /versatile_mem_ctrl/trunk/rtl/verilog/
2 initial unneback 5487d 06h /versatile_mem_ctrl/trunk/rtl/verilog/

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