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[/] [versatile_mem_ctrl/] [trunk/] [rtl/] [verilog/] - Rev 33

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Rev Log message Author Age Path
33 work for limited test case, no cke inhibit for fifo empty unneback 5263d 23h /versatile_mem_ctrl/trunk/rtl/verilog/
32 Updated the testbench to match the new wishbone interface. mikaeljf 5267d 03h /versatile_mem_ctrl/trunk/rtl/verilog/
31 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5268d 20h /versatile_mem_ctrl/trunk/rtl/verilog/
30 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5268d 20h /versatile_mem_ctrl/trunk/rtl/verilog/
28 Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'. mikaeljf 5272d 22h /versatile_mem_ctrl/trunk/rtl/verilog/
27 unneback 5276d 14h /versatile_mem_ctrl/trunk/rtl/verilog/
26 compiles OK, not simulated unneback 5278d 13h /versatile_mem_ctrl/trunk/rtl/verilog/
25 unneback 5278d 15h /versatile_mem_ctrl/trunk/rtl/verilog/
24 Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions. mikaeljf 5279d 03h /versatile_mem_ctrl/trunk/rtl/verilog/
23 Removed redundant code. mikaeljf 5286d 19h /versatile_mem_ctrl/trunk/rtl/verilog/
22 Updated the Altera timing constraints file, also minor updates of defines file and Makefile. mikaeljf 5288d 15h /versatile_mem_ctrl/trunk/rtl/verilog/
21 Updated the Altera timing constraints file (.sdc). mikaeljf 5292d 18h /versatile_mem_ctrl/trunk/rtl/verilog/
20 Minor update of sdc-file. mikaeljf 5294d 20h /versatile_mem_ctrl/trunk/rtl/verilog/
19 Added do-file for Modelsim waveform viewer. mikaeljf 5301d 00h /versatile_mem_ctrl/trunk/rtl/verilog/
18 Updated the rtl/verilog Makefile and the bench Makefile. mikaeljf 5301d 21h /versatile_mem_ctrl/trunk/rtl/verilog/
17 Modified rtl Makefile and tb_defines.v mikaeljf 5304d 20h /versatile_mem_ctrl/trunk/rtl/verilog/
16 Added fizzim.pl mikaeljf 5304d 21h /versatile_mem_ctrl/trunk/rtl/verilog/
15 Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera. mikaeljf 5305d 21h /versatile_mem_ctrl/trunk/rtl/verilog/
13 Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback. mikaeljf 5396d 02h /versatile_mem_ctrl/trunk/rtl/verilog/
11 Initial version with support for DDR mikaeljf 5406d 15h /versatile_mem_ctrl/trunk/rtl/verilog/

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