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[/] [versatile_mem_ctrl/] [trunk/] [rtl/] [verilog/] - Rev 37

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Rev Log message Author Age Path
37 unneback 5326d 02h /versatile_mem_ctrl/trunk/rtl/verilog/
36 unneback 5326d 02h /versatile_mem_ctrl/trunk/rtl/verilog/
35 work for limited test case unneback 5326d 10h /versatile_mem_ctrl/trunk/rtl/verilog/
34 added unneback 5326d 10h /versatile_mem_ctrl/trunk/rtl/verilog/
33 work for limited test case, no cke inhibit for fifo empty unneback 5326d 12h /versatile_mem_ctrl/trunk/rtl/verilog/
32 Updated the testbench to match the new wishbone interface. mikaeljf 5329d 16h /versatile_mem_ctrl/trunk/rtl/verilog/
31 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5331d 09h /versatile_mem_ctrl/trunk/rtl/verilog/
30 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5331d 09h /versatile_mem_ctrl/trunk/rtl/verilog/
28 Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'. mikaeljf 5335d 11h /versatile_mem_ctrl/trunk/rtl/verilog/
27 unneback 5339d 03h /versatile_mem_ctrl/trunk/rtl/verilog/
26 compiles OK, not simulated unneback 5341d 02h /versatile_mem_ctrl/trunk/rtl/verilog/
25 unneback 5341d 04h /versatile_mem_ctrl/trunk/rtl/verilog/
24 Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions. mikaeljf 5341d 16h /versatile_mem_ctrl/trunk/rtl/verilog/
23 Removed redundant code. mikaeljf 5349d 08h /versatile_mem_ctrl/trunk/rtl/verilog/
22 Updated the Altera timing constraints file, also minor updates of defines file and Makefile. mikaeljf 5351d 04h /versatile_mem_ctrl/trunk/rtl/verilog/
21 Updated the Altera timing constraints file (.sdc). mikaeljf 5355d 07h /versatile_mem_ctrl/trunk/rtl/verilog/
20 Minor update of sdc-file. mikaeljf 5357d 09h /versatile_mem_ctrl/trunk/rtl/verilog/
19 Added do-file for Modelsim waveform viewer. mikaeljf 5363d 13h /versatile_mem_ctrl/trunk/rtl/verilog/
18 Updated the rtl/verilog Makefile and the bench Makefile. mikaeljf 5364d 10h /versatile_mem_ctrl/trunk/rtl/verilog/
17 Modified rtl Makefile and tb_defines.v mikaeljf 5367d 09h /versatile_mem_ctrl/trunk/rtl/verilog/

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