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[/] [versatile_mem_ctrl/] [trunk/] [rtl/] [verilog/] - Rev 38

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Rev Log message Author Age Path
38 casex in rw state to save logic unneback 5294d 06h /versatile_mem_ctrl/trunk/rtl/verilog/
37 unneback 5294d 21h /versatile_mem_ctrl/trunk/rtl/verilog/
36 unneback 5294d 21h /versatile_mem_ctrl/trunk/rtl/verilog/
35 work for limited test case unneback 5295d 05h /versatile_mem_ctrl/trunk/rtl/verilog/
34 added unneback 5295d 05h /versatile_mem_ctrl/trunk/rtl/verilog/
33 work for limited test case, no cke inhibit for fifo empty unneback 5295d 07h /versatile_mem_ctrl/trunk/rtl/verilog/
32 Updated the testbench to match the new wishbone interface. mikaeljf 5298d 11h /versatile_mem_ctrl/trunk/rtl/verilog/
31 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5300d 04h /versatile_mem_ctrl/trunk/rtl/verilog/
30 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5300d 04h /versatile_mem_ctrl/trunk/rtl/verilog/
28 Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'. mikaeljf 5304d 06h /versatile_mem_ctrl/trunk/rtl/verilog/
27 unneback 5307d 22h /versatile_mem_ctrl/trunk/rtl/verilog/
26 compiles OK, not simulated unneback 5309d 21h /versatile_mem_ctrl/trunk/rtl/verilog/
25 unneback 5309d 23h /versatile_mem_ctrl/trunk/rtl/verilog/
24 Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions. mikaeljf 5310d 11h /versatile_mem_ctrl/trunk/rtl/verilog/
23 Removed redundant code. mikaeljf 5318d 03h /versatile_mem_ctrl/trunk/rtl/verilog/
22 Updated the Altera timing constraints file, also minor updates of defines file and Makefile. mikaeljf 5319d 23h /versatile_mem_ctrl/trunk/rtl/verilog/
21 Updated the Altera timing constraints file (.sdc). mikaeljf 5324d 02h /versatile_mem_ctrl/trunk/rtl/verilog/
20 Minor update of sdc-file. mikaeljf 5326d 04h /versatile_mem_ctrl/trunk/rtl/verilog/
19 Added do-file for Modelsim waveform viewer. mikaeljf 5332d 08h /versatile_mem_ctrl/trunk/rtl/verilog/
18 Updated the rtl/verilog Makefile and the bench Makefile. mikaeljf 5333d 05h /versatile_mem_ctrl/trunk/rtl/verilog/

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