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[/] [versatile_mem_ctrl/] [trunk/] [rtl/] [verilog/] - Rev 42

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Rev Log message Author Age Path
42 added pipeline stage for egress FIFO readot unneback 5184d 07h /versatile_mem_ctrl/trunk/rtl/verilog/
41 Added two alternate data capture functions. mikaeljf 5184d 14h /versatile_mem_ctrl/trunk/rtl/verilog/
40 updated fifo interfaces with re/rd and we/wr unneback 5184d 21h /versatile_mem_ctrl/trunk/rtl/verilog/
39 updated FIFO and SDR 16 unneback 5185d 09h /versatile_mem_ctrl/trunk/rtl/verilog/
38 casex in rw state to save logic unneback 5187d 17h /versatile_mem_ctrl/trunk/rtl/verilog/
37 unneback 5188d 07h /versatile_mem_ctrl/trunk/rtl/verilog/
36 unneback 5188d 07h /versatile_mem_ctrl/trunk/rtl/verilog/
35 work for limited test case unneback 5188d 15h /versatile_mem_ctrl/trunk/rtl/verilog/
34 added unneback 5188d 15h /versatile_mem_ctrl/trunk/rtl/verilog/
33 work for limited test case, no cke inhibit for fifo empty unneback 5188d 17h /versatile_mem_ctrl/trunk/rtl/verilog/
32 Updated the testbench to match the new wishbone interface. mikaeljf 5191d 21h /versatile_mem_ctrl/trunk/rtl/verilog/
31 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5193d 14h /versatile_mem_ctrl/trunk/rtl/verilog/
30 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5193d 14h /versatile_mem_ctrl/trunk/rtl/verilog/
28 Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'. mikaeljf 5197d 16h /versatile_mem_ctrl/trunk/rtl/verilog/
27 unneback 5201d 08h /versatile_mem_ctrl/trunk/rtl/verilog/
26 compiles OK, not simulated unneback 5203d 07h /versatile_mem_ctrl/trunk/rtl/verilog/
25 unneback 5203d 10h /versatile_mem_ctrl/trunk/rtl/verilog/
24 Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions. mikaeljf 5203d 21h /versatile_mem_ctrl/trunk/rtl/verilog/
23 Removed redundant code. mikaeljf 5211d 14h /versatile_mem_ctrl/trunk/rtl/verilog/
22 Updated the Altera timing constraints file, also minor updates of defines file and Makefile. mikaeljf 5213d 09h /versatile_mem_ctrl/trunk/rtl/verilog/

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